About
I am a founding member of technical staff at Ricursive Intelligence, working on AI for chip design. Previously, I was a member of the AlphaChip team at Google Brain and DeepMind, contributing to foundational research on AI-driven chip design published in Nature. My work spans differentiable programming, physical design, and timing analysis for semiconductor chip design.
Experience
AI for Chip Design.
Member of Google DeepMind GenAI's AI for AI chip team. Advanced the state of the art in AI/ML for semiconductor design through differentiable and learning-based approaches to physical design and timing analysis.
Contributed to foundational research on ML-driven chip design as part of Google Brain's ML for Systems team. Designed a novel graph convolutional architecture enabling generalization across chip placement tasks — a core innovation of AlphaChip.
Designed and delivered scalable infrastructure for a two-tower deep learning retrieval system, improving ad latency and relevance.
Education
Supervisor: Prof. Farinaz Koushanfar (UC San Diego)
Selected Publications & Patents
- Mirhoseini, Goldie, Yazgan, Jiang, Songhori, E., et al. "A graph placement methodology for fast chip design." Nature 594 (2021): 207–212.
- Songhori, E., Wang, Mirhoseini, Goldie, et al. "Alignment Cost for Integrated Circuit Placement." U.S. Patent Application 17/890,370 (2024).
- Zhang, Safeen, Mirhoseini, Goldie, Songhori, E. "Full-stack hardware accelerator search." U.S. Patent Application 18/285,578 (2024).
- Goldie, Mirhoseini, Songhori, E., Jiang, Wang, et al. "Generating integrated circuit placements using neural networks." U.S. Patent Application 17/555,085 (2022).
- Riazi, Weinert, Tkachenko, Songhori, E., Schneider, Koushanfar. "Chameleon: A hybrid secure computation framework for ML applications." AsiaCCS (2018).
- Songhori, E., Hussain, Sadeghi, Schneider, Koushanfar. "TinyGarble: Highly compressed and scalable sequential garbled circuits." IEEE S&P (2015).